Final Workshop Final Workshop Programme Session Theme Session G1 Summary Opening P1 Main Papers DPR of Loop Accelerators (IEEE VLSI) P2 k-means on FPGA via OpenCL (IEEE Access) P3 An Overview on Binary Translation (ACM CSUR) L1 Coarse-Grained Reconfigurable Computing with the Versat Architecture (Electronics) L2 A Full Featured Configurable Accelerator for Object Detection With YOLO Discussion Break #1 P4 Technical Content #1 Binary Translation Framework (IEEE Micro, FPL2020, and DATE2020) P5 Transparent CPU-FPGA Control Flow Transfer in HPC P6 Dataflow Graph Analysis P7 Memory Pattern Analysis P8 CrispyHDL Discussion Break #2 L4 Technical Content #2 Versat Architecture, J.Lopes, PhD candidate L5 Versat Compiler, R. Teixeira, PhD candidate L6 RNN on Versat, B. Joudat, PhD candidate L7 IOb-SoC, P. Miranda, former MSc student, now engineer at IObundle Session Slides G1. Opening P1. DPR of Loop Accelerators (IEEE VLSI) P2. k-means on FPGA via OpenCL (IEEE Access) P3. An Overview on Binary Translation (ACM CSUR) L1. Coarse-Grained Reconfigurable Computing with the Versat Architecture (Electronics) L2. A Full Featured Configurable Accelerator for Object Detection With YOLO P4. Binary Translation Framework (IEEE Micro, FPL2020, and DATE2020) P5. Transparent CPU-FPGA Control Flow Transfer in HPC P6. Dataflow Graph Analysis P7. Memory Pattern Analysis P8. CrispyHDL L4. Versat Architecture L5. Versat Compiler L6. RNN on Versat L7. IOb-SoC Session Presentations G1. Summary P1. DPR of Loop Accelerators (IEEE VLSI) P2. k-means on FPGA via OpenCL (IEEE Access) L1. Coarse-Grained Reconfigurable Computing with the Versat Architecture (Electronics) L2. A Full Featured Configurable Accelerator for Object Detection With YOLO P4. Binary Translation Framework (IEEE Micro, FPL2020, and DATE2020) P5. Transparent CPU-FPGA Control Flow Transfer in HPC P6. Dataflow Graph Analysis P7. Memory Pattern Analysis P8. CrispyHDL L4. Versat Architecture L5. Versat Compiler L6. RNN on Versat L7. IOb-SoC