What is PEPCC?

The domains of embedded systems and high-performance computing (HPC) are usually seen as distant, but some of their requirements are converging: a modern ES runs complex algorithms with high computational power; the power consumption of ever larger HPC systems requires new levels of power efficiency.

Embedded systems have adopted heterogeneous architectures, often based on reconfigurable accelerators like FPGAs or Coarse-Grained Reconfigurable Arrays (CGRAs), because they combine hardware specialization (improving performance and power efficiency) with adaptability at run-time. A similar trend towards heterogeneity is observed in HPC systems with GPUs as accelerators: HPC stakeholders have identified several challenges related to auto-tuning and self adapting systems, and power-aware resource management, matching the trends identified by ES stakeholders on the relevance of heterogeneous accelerators.

The goal of this project is to devise efficient techniques for dynamically mapping computations extracted from execution behavior to the resources of specialized reconfigurable accelerators. The techniques will identify at runtime the hotspots of program execution. They are then optimized and mapped to CGRAs tailored to the actual set of executing kernels. Whenever one hotspot needs to be executed, the accelerator is transparently invoked. The use of specialized CGRAs reduces resource usage and improves performance. The project will apply these concepts in the ES and HPC domains.

Project Information

  • Start Date: 1st of October, 2018
  • Duration: 2.5 years
  • Project Reference: PTDC/EEI-HAC/30848/2017
  • Call: 02/SAICT/2017
  • Funded Under: FCT (Fundação para a Ciência e a Tecnologia)
  • Total Funding: 239.591,66€

Project keywords: reconfigurable computing, power-efficient computing, embedded systems, HPC (high-performance computing)


Principal Investigator
João Canas Ferreira
Co-Principal Investigator
João M.P. Cardoso