Media & Resources

Media & Resources

Interactive Web-Demo for Binary Translation Framework!

30/19/2020

You can find our web based front end for demonstration of the Binary Translation Framework now live at http://specs.fe.up.pt/tools/btf/ !

Current features include:

  • Static analysis of a given ELF file for the MicroBlaze processor
  • Detection of Frequent Sequences and Basic Blocks
  • Graphical display of the detected regions and statistical data

Future features will include dynamic analysis, other instruction sets, and generation of specialized hardware in Verilog HDL form.

Binary Translation Framework Demo @ DATE 2020

This presentation was given as a Demo Booth at the DATE 2020 conference. It summarizes the capabilities of the Binary Translation Framework at the date of March 2020. The framework at this point was capable of interpreting static and trace instruction streams for MicroBlaze 32-bit and ARMv8 processors, and could thereafter detect binary segments of several types, and generate the respective CDFGs.

Binary Translation Framework Demo @ FPL 2020

This presentation was given as a Demo Booth at the FPL 2020 conference. It summarizes the capabilities of the Binary Translation Framework at the date of August of 2020. The framework capabilities included support for decoding additional ARMv8 instructions, preliminary support for RISC-V (32iam) instruction streams, as well as generation of HDL (Verilog) from the detected binary segments. To implement the binary-to-source capabilities, the BTF relies on a custom ANTLR4 grammar, and transformations over the generated ASTs representing the instruction stream arithmetic and operations.

Conference Presentation @ FPT 2021

By using Dynamic Binary Translation, instruction traces from pre-compiled applications can be offloaded, at runtime, to FPGA-based accelerators, such as Coarse-Grained Loop Accelerators, in a transparent way. However, scheduling onto coarse-grain accelerators is challenging, with two of current known issues being the density of computations that can be mapped, and the effects of memory accesses on performance. Using an in-house framework for analysis of instruction traces, we explore the effect of different window sizes when applying list scheduling, to map the window operations to a coarse-grain loop accelerator model that has been previously experimentally validated. Find the paper at: https://ieeexplore.ieee.org/document/9609868