This repository holds the implementation for the Binary Translation infrastructure that is the backbone of the automated hardware generation infrastructure. Automated hardware generation is the overarching concept that guides the design of tools supported by the techniques outlined in Activities 1 and 2, which you can find in the Project Description page.
Architectures and libraries of hardware modules written in Chisel
https://github.com/specs-feup/specs-chisel
0 forks.
0 stars.
0 open issues.
This repository holds the implementation for the Binary Translation infrastructure that is the backbone of the automated hardware generation infrastructure. Automated hardware generation is the overarching concept that guides the design of tools supported by the techniques outlined in Activities 1 and 2, which you can find in the Project Description page.
Hardware-related libraries and applications
https://github.com/specs-feup/specs-hw
0 forks.
5 stars.
0 open issues.
This repository holds an implementation of a parametrizable multicore system equipped with CGRAs. The RISC-V implementation is fully custom, and the CGRAs employed are instances of the Versat CGRA. The several CGRAs are shared among the RISC-V cores, and can be programmed at high level via assembly or C++. Targeting the Versat CGRA with binary translation is the objective of Activity 3, which you can find in the Project Description page.
RISC-V System on Chip Template Based on the picorv32 Processor
https://github.com/jjts/iob-soc
0 forks.
0 stars.
0 open issues.
