Timeline

PEPCC Timeline (2018 - Ongoing)

2020
Creation of Code Repository for Chisel-based Hardware Architectures

Creation of GitHub repository for exploration of hardware architectures for accelerators, CGRA designs, or other modules, targetable by the compilation and transformation tools in the Binary Translation Framework repository.

See Repositories pageSee repository on GitHub

Demo Booth at FPL2020 (Virtual)
Demo Booth at FPL2020 (Virtual)

Nuno Paulino, João C. Ferreira, João Bispo, and João M.P. Cardoso, 2020, “Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework”, Demo Booth and Short Paper in Field Programmable Logic and Applications (FPL), August 31 – September 4

View Demo VideoView Poster

View AbstractView on IEEEXplore®

Binary Translation Framework Update #2

Tagged version v0.2 of Binary Translation Framework capable of generating HDL from the developed ANTLR based intermediate representations of the detected binary segments, for MicroBlaze and ARMv8!

Journal Publication #8
Journal Publication #8

N. Paulino, J. C. Ferreira and J. M. P. Cardoso, “Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets“, in IEEE Access, vol. 8, pp. 152286-152304, 2020, doi: 10.1109/ACCESS.2020.3017552.

View on IEEEXplore®

Data #3

Nuno Paulino, 2020, “A Batch of Integer Data Sets for Clustering Algorithms”

View on ResearchGate

Utility #1
Utility #1

Nuno Paulino, 2020, “A Generator of Randomly Correlated N-Dimentional Clusters

View on ResearchGate

Journal Publication #7

Mario Véstias, Rui P. Duarte, José T. de Sousa, Horácio C. Neto,”A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs“, in IEEE Access, vol. 8, pp. 107229-107243, 08 June 2020

View on IEEEXplore®

Journal Publication #6

Mario Véstias, Rui P. Duarte, José T. de Sousa, Horácio C. Neto, “Moving Deep Learning to the Edge“, Algorithms 2020, 13, 12, 18 May 2020, https://doi.org/10.3390/a13050125

View on MDPI®

Journal Publication #5

Mário Véstias, Rui P. Duarte, José T. de Sousa, Horácio C. Neto, “A fast and scalable architecture to run convolutional neural networks in low density FPGAs”, Microprocessors and Microsystems, Volume 77, 2020, 14 May 2020

View on Elsevier

Journal Publication #4

Valter Mário, João D. Lopes, Mario Véstias, José T. de Sousa, “Implementing CNNs Using a Linear Array of Full Mesh CGRAs“, In: Rincón F., Barba J., So H., Diniz P., Caba J. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2020. Lecture Notes in Computer Science, vol 12083. Springer, Cham.

View on Springer®

Demo Booth at DATE2020 (Virtual)
Demo Booth at DATE2020 (Virtual)

Nuno Paulino and João C. Ferreira, 2020, “A Binary Translation Framework for Automated Hardware Generation”, Demo Booth at Design Automation and Test in Europe (DATE), Grenoble, France, 9 – 13 March 2020

View Demo VideoView on IEEEXplore®

View PosterView Abstract

Short Keynote

Presentation of a short keynote regarding published journal paper “Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey“, at the 16th edition of national conference REC, held at the “Instituto Superior Técnico”, Lisbon.

View Conference PageView Presentation

Data #2

Nuno Paulino, João C. Ferreira, and João M. P. Cardoso, “A Breakdown of Binary Acceleration Approaches and Systems″, 2020

View on ResearchGate

Data #1
Data #1

Nuno Paulino, João C. Ferreira, and João M. P. Cardoso, “A Dataset for Desktop Processor Characteristics from 1970 to 2019″, 2020

View on ResearchGate

Journal Publication #3
Journal Publication #3

Nuno Paulino, João Canas Ferreira, and João M. P. Cardoso. 2020. “Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey”. ACM Comput. Surv. 53, 1, Article 6 (February 2020), 36 pages. DOI:https://doi.org/10.1145/3369764

View on ACM Digital Library

Binary Translation Framework Update #1
Binary Translation Framework Update #1

Tagged version v0.1 of Binary Translation Framework capable of generating graph visualizations and profile data for detected binary instruction segments for 32-bit MicroBlaze and ARMv8 ISAs. Supported segments include static and trace frequent instruction sequences, and static basic blocks!

2019
Conference Publication #2
Conference Publication #2

M. P. Véstias, R. Policarpo Duarte, J. T. de Sousa and H. Neto, “Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA”, 2019 29th International Conference on Field Programmable Logic and Applications (FPL), Barcelona, Spain, 2019, pp. 350-353. doi: 10.1109/FPL.2019.00062

View on IEEEXplore®

Journal Publication #2

Mario Véstias, Rui P. Duarte, José T. de Sousa, Horácio C. Neto, “Fast Convolutional Neural Networks in Low Density FPGAs Using Zero-Skipping and Weight Pruning“, Electronics 2019, 8, 1321

View on MDPI

Creation of Code Repository for Binary Translation Tools

Creation of GitHub repository for implementation of Binary Translation Framework.

See Repositories pageSee repository on GitHub

Conference Publication #1
Conference Publication #1

L. Fiolhais, F. Gonçalves, R. P. Duarte, M. Véstias and J. T. de Sousa, “Low Energy Heterogeneous Computing with Multiple RISC-V and CGRA Cores”, 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 2019, pp. 1-5. doi: 10.1109/ISCAS.2019.8702538

View on IEEEXplore®

Short Keynote

Presentation of a short keynote regarding published journal paper “Dynamic Partial Reconfiguration of Customized Single-Row Accelerators”, at the 15th edition of national conference REC, held at the University of Minho, Guimarães.

View Conference PageView Presentation

2018
Journal Publication #1
Journal Publication #1

N. M. C. Paulino, J. C. Ferreira and J. M. P. Cardoso, “Dynamic Partial Reconfiguration of Customized Single-Row Accelerators”, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 1, pp. 116-125, Jan. 2019.

View on IEEEXplore®

Project Start

Start of project!