Timeline PEPCC Timeline (2018 - Ongoing) 2020 November 11 Creation of Code Repository for Chisel-based Hardware ArchitecturesCreation of GitHub repository for exploration of hardware architectures for accelerators, CGRA designs, or other modules, targetable by the compilation and transformation tools in the Binary Translation Framework repository. See Repositories page – See repository on GitHubSeptember 9 Demo Booth at FPL2020 (Virtual)Nuno Paulino, João C. Ferreira, João Bispo, and João M.P. Cardoso, 2020, “Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework”, Demo Booth and Short Paper in Field Programmable Logic and Applications (FPL), August 31 – September 4 View Demo Video – View Poster View Abstract – View on IEEEXplore® August 20 Binary Translation Framework Update #2Tagged version v0.2 of Binary Translation Framework capable of generating HDL from the developed ANTLR based intermediate representations of the detected binary segments, for MicroBlaze and ARMv8! August 18 Journal Publication #8N. Paulino, J. C. Ferreira and J. M. P. Cardoso, “Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets“, in IEEE Access, vol. 8, pp. 152286-152304, 2020, doi: 10.1109/ACCESS.2020.3017552. View on IEEEXplore® July 30 Data #3Nuno Paulino, 2020, “A Batch of Integer Data Sets for Clustering Algorithms” View on ResearchGate July 20 Utility #1Nuno Paulino, 2020, “A Generator of Randomly Correlated N-Dimentional Clusters” View on ResearchGate June 8 Journal Publication #7Mario Véstias, Rui P. Duarte, José T. de Sousa, Horácio C. Neto,”A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs“, in IEEE Access, vol. 8, pp. 107229-107243, 08 June 2020 View on IEEEXplore® May 18 Journal Publication #6Mario Véstias, Rui P. Duarte, José T. de Sousa, Horácio C. Neto, “Moving Deep Learning to the Edge“, Algorithms 2020, 13, 12, 18 May 2020, https://doi.org/10.3390/a13050125 View on MDPI® May 14 Journal Publication #5Mário Véstias, Rui P. Duarte, José T. de Sousa, Horácio C. Neto, “A fast and scalable architecture to run convolutional neural networks in low density FPGAs”, Microprocessors and Microsystems, Volume 77, 2020, 14 May 2020 View on Elsevier March 25 Journal Publication #4Valter Mário, João D. Lopes, Mario Véstias, José T. de Sousa, “Implementing CNNs Using a Linear Array of Full Mesh CGRAs“, In: Rincón F., Barba J., So H., Diniz P., Caba J. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2020. Lecture Notes in Computer Science, vol 12083. Springer, Cham. View on Springer® Page 1 of 3 1 2 3 »