PEPCC Timeline (2018 - Ongoing)

November 11

Creation of Code Repository for Chisel-based Hardware Architectures

Creation of GitHub repository for exploration of hardware architectures for accelerators, CGRA designs, or other modules, targetable by the compilation and transformation tools in the Binary Translation Framework repository. See Repositories pageSee repository on GitHub
September 9

Demo Booth at FPL2020 (Virtual)

Demo Booth at FPL2020 (Virtual)

Nuno Paulino, João C. Ferreira, João Bispo, and João M.P. Cardoso, 2020, “Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework”, Demo Booth and Short Paper in Field Programmable Logic and Applications (FPL), August 31 – September 4

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August 20

Binary Translation Framework Update #2

Tagged version v0.2 of Binary Translation Framework capable of generating HDL from the developed ANTLR based intermediate representations of the detected binary segments, for MicroBlaze and ARMv8!

August 18

Journal Publication #8

Journal Publication #8

N. Paulino, J. C. Ferreira and J. M. P. Cardoso, “Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets“, in IEEE Access, vol. 8, pp. 152286-152304, 2020, doi: 10.1109/ACCESS.2020.3017552.

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July 30

Data #3

Nuno Paulino, 2020, “A Batch of Integer Data Sets for Clustering Algorithms”

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July 20

Utility #1

Utility #1

Nuno Paulino, 2020, “A Generator of Randomly Correlated N-Dimentional Clusters

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June 8

Journal Publication #7

Mario Véstias, Rui P. Duarte, José T. de Sousa, Horácio C. Neto,”A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs“, in IEEE Access, vol. 8, pp. 107229-107243, 08 June 2020

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May 18

Journal Publication #6

Mario Véstias, Rui P. Duarte, José T. de Sousa, Horácio C. Neto, “Moving Deep Learning to the Edge“, Algorithms 2020, 13, 12, 18 May 2020, https://doi.org/10.3390/a13050125

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May 14

Journal Publication #5

Mário Véstias, Rui P. Duarte, José T. de Sousa, Horácio C. Neto, “A fast and scalable architecture to run convolutional neural networks in low density FPGAs”, Microprocessors and Microsystems, Volume 77, 2020, 14 May 2020

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March 25

Journal Publication #4

Valter Mário, João D. Lopes, Mario Véstias, José T. de Sousa, “Implementing CNNs Using a Linear Array of Full Mesh CGRAs“, In: Rincón F., Barba J., So H., Diniz P., Caba J. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2020. Lecture Notes in Computer Science, vol 12083. Springer, Cham.

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