PEPCC Timeline (2018 - Ongoing)
Nuno Paulino, João C. Ferreira, João Bispo, and João M.P. Cardoso, 2020, “Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework”, Demo Booth and Short Paper in Field Programmable Logic and Applications (FPL), August 31 – September 4
N. Paulino, J. C. Ferreira and J. M. P. Cardoso, “Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets“, in IEEE Access, vol. 8, pp. 152286-152304, 2020, doi: 10.1109/ACCESS.2020.3017552.
Nuno Paulino, 2020, “A Generator of Randomly Correlated N-Dimentional Clusters”
Nuno Paulino and João C. Ferreira, 2020, “A Binary Translation Framework for Automated Hardware Generation”, Demo Booth at Design Automation and Test in Europe (DATE), Grenoble, France, 9 – 13 March 2020
Nuno Paulino, João C. Ferreira, and João M. P. Cardoso, “A Dataset for Desktop Processor Characteristics from 1970 to 2019″, 2020
Nuno Paulino, João Canas Ferreira, and João M. P. Cardoso. 2020. “Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey”. ACM Comput. Surv. 53, 1, Article 6 (February 2020), 36 pages. DOI:https://doi.org/10.1145/3369764
Tagged version v0.1 of Binary Translation Framework capable of generating graph visualizations and profile data for detected binary instruction segments for 32-bit MicroBlaze and ARMv8 ISAs. Supported segments include static and trace frequent instruction sequences, and static basic blocks!
M. P. Véstias, R. Policarpo Duarte, J. T. de Sousa and H. Neto, “Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA”, 2019 29th International Conference on Field Programmable Logic and Applications (FPL), Barcelona, Spain, 2019, pp. 350-353. doi: 10.1109/FPL.2019.00062
L. Fiolhais, F. Gonçalves, R. P. Duarte, M. Véstias and J. T. de Sousa, “Low Energy Heterogeneous Computing with Multiple RISC-V and CGRA Cores”, 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 2019, pp. 1-5. doi: 10.1109/ISCAS.2019.8702538
N. M. C. Paulino, J. C. Ferreira and J. M. P. Cardoso, “Dynamic Partial Reconfiguration of Customized Single-Row Accelerators”, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 1, pp. 116-125, Jan. 2019.