Timeline

PEPCC Timeline (2018 - Ongoing)

2020
March 9

Demo Booth at DATE2020 (Virtual)

Demo Booth at DATE2020 (Virtual)
Nuno Paulino and João C. Ferreira, 2020, “A Binary Translation Framework for Automated Hardware Generation”, Demo Booth at Design Automation and Test in Europe (DATE), Grenoble, France, 9 – 13 March 2020 View Demo VideoView on IEEEXplore® View PosterView Abstract
February 10

Short Keynote

Presentation of a short keynote regarding published journal paper “Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey“, at the 16th edition of national conference REC, held at the “Instituto Superior Técnico”, Lisbon.

View Conference PageView Presentation

February 9

Data #2

Nuno Paulino, João C. Ferreira, and João M. P. Cardoso, “A Breakdown of Binary Acceleration Approaches and Systems″, 2020

View on ResearchGate

February 9

Data #1

Data #1

Nuno Paulino, João C. Ferreira, and João M. P. Cardoso, “A Dataset for Desktop Processor Characteristics from 1970 to 2019″, 2020

View on ResearchGate

February 8

Journal Publication #3

Journal Publication #3

Nuno Paulino, João Canas Ferreira, and João M. P. Cardoso. 2020. “Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey”. ACM Comput. Surv. 53, 1, Article 6 (February 2020), 36 pages. DOI:https://doi.org/10.1145/3369764

View on ACM Digital Library

January 23

Binary Translation Framework Update #1

Binary Translation Framework Update #1

Tagged version v0.1 of Binary Translation Framework capable of generating graph visualizations and profile data for detected binary instruction segments for 32-bit MicroBlaze and ARMv8 ISAs. Supported segments include static and trace frequent instruction sequences, and static basic blocks!

2019
November 7

Conference Publication #2

Conference Publication #2

M. P. Véstias, R. Policarpo Duarte, J. T. de Sousa and H. Neto, “Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA”, 2019 29th International Conference on Field Programmable Logic and Applications (FPL), Barcelona, Spain, 2019, pp. 350-353. doi: 10.1109/FPL.2019.00062

View on IEEEXplore®

September 19

Journal Publication #2

Mario Véstias, Rui P. Duarte, José T. de Sousa, Horácio C. Neto, “Fast Convolutional Neural Networks in Low Density FPGAs Using Zero-Skipping and Weight Pruning“, Electronics 2019, 8, 1321

View on MDPI

September 17

Creation of Code Repository for Binary Translation Tools

Creation of GitHub repository for implementation of Binary Translation Framework.

See Repositories pageSee repository on GitHub

May 1

Conference Publication #1

Conference Publication #1

L. Fiolhais, F. Gonçalves, R. P. Duarte, M. Véstias and J. T. de Sousa, “Low Energy Heterogeneous Computing with Multiple RISC-V and CGRA Cores”, 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 2019, pp. 1-5. doi: 10.1109/ISCAS.2019.8702538

View on IEEEXplore®