Project Publications

Publications in International Peer-Reviewed Journals

Nuno Paulino, João C. Ferreira and João M. P. Cardoso, “Dynamic Partial Reconfiguration of Customized Single-Row Accelerators“, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 1, pp. 116-125, Jan. 2019.
Mario Véstias, Rui P. Duarte, José T. de Sousa, Horácio C. Neto, “Fast Convolutional Neural Networks in Low Density FPGAs Using Zero-Skipping and Weight Pruning“, Electronics 2019, 8, 1321, 9 Nov. 2019
Nuno Paulino, João C. Ferreira, and João M. P. Cardoso, 2020. “Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey“, ACM Computing Surveys (CSUR) 53, vol. 1, Article 6 (February 2020), 36 pages
Mario Véstias, Rui P. Duarte, José T. de Sousa, Horácio C. Neto,”A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs“, in IEEE Access, vol. 8, pp. 107229-107243, 08 June 2020
Valter Mário, João D. Lopes, Mario Véstias, José T. de Sousa, “Implementing CNNs Using a Linear Array of Full Mesh CGRAs“, In: Rincón F., Barba J., So H., Diniz P., Caba J. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications (ARC), 25 March 2020, Lecture Notes in Computer Science, vol 12083. Springer, Cham.
Mário Véstias, Rui P. Duarte, José T. de Sousa, Horácio C. Neto, “A fast and scalable architecture to run convolutional neural networks in low density FPGAs“, Microprocessors and Microsystems, Volume 77, 2020, 14 May 2020
Mário Véstias, Rui P. Duarte, José T. de Sousa, Horácio C. Neto, “Moving Deep Learning to the Edge“, Algorithms 2020, 13, 12, 18 May 2020
Nuno Paulino, João C. Ferreira, and João M. P. Cardoso, “Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets,” in IEEE Access, vol. 8, pp. 152286-152304, 18 August 2020

Publications in International Peer-Reviewed Conferences

Luís Fiolhais, Fernando Gonçalves, Rui P. Duarte, Mário Véstias and Jośe T. de Sousa, “Low Energy Heterogeneous Computing with Multiple RISC-V and CGRA Cores,” 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 2019, pp. 1-5. doi: 10.1109/ISCAS.2019.8702538
Mario Véstias, Rui P. Duarte, José T. de Sousa, Horácio C. Neto, “Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA“, 2019 29th International Conference on Field Programmable Logic and Applications (FPL), Barcelona, Spain, 2019, pp. 350-353, doi: 10.1109/FPL.2019.00062.

Published Master's Thesis

António Charana, “Development Environment for a RISC-V Processor“, July 27th 2020, Instituto Superior Técnico de Lisboa, João T. de Sousa (Supervisor)
André Merendeira, “Verilog PNG Encoder“, September 25th 2020, Instituto Superior Técnico de Lisboa, João T. de Sousa (Supervisor)
Daniel Granhão, “Transparent control flow transfer between CPU and Intel FPGAs“, July 17th 2019, Faculdade de Engenharia da Universidade do Porto, João Canas Ferreira (Supervisor)