{"id":213,"date":"2019-01-15T10:15:29","date_gmt":"2019-01-15T10:15:29","guid":{"rendered":"http:\/\/pepcc.inesctec.pt\/?page_id=213"},"modified":"2020-11-05T09:21:01","modified_gmt":"2020-11-05T09:21:01","slug":"timeline","status":"publish","type":"page","link":"https:\/\/pepcc.inesctec.pt\/?page_id=213","title":{"rendered":"Timeline"},"content":{"rendered":"\t\t\t\n\t\t\t
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PEPCC Timeline (2018 - Ongoing)<\/h1><\/div><\/div>\t\t\t\t
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2020<\/span><\/div><\/div>
November 11<\/div><\/div>
<\/i><\/div>
<\/div>
Creation of Code Repository for Chisel-based Hardware Architectures<\/div>
Creation of GitHub repository for exploration of hardware architectures for accelerators, CGRA designs, or other modules, targetable by the compilation and transformation tools in the Binary Translation Framework<\/a> repository.\r\n\r\nSee Repositories page<\/a> – See repository on GitHub<\/a><\/div><\/div><\/div>
September 9<\/div><\/div>
<\/i><\/div>
<\/div>
Demo Booth at FPL2020 (Virtual)<\/div>
\"Demo<\/a><\/div>

Nuno Paulino, Jo\u00e3o C. Ferreira, Jo\u00e3o Bispo, and Jo\u00e3o M.P. Cardoso, 2020, “Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework”<\/em>, Demo Booth and Short Paper in Field Programmable Logic and Applications (FPL), August 31 – September 4<\/p>\n

View Demo Video<\/a> – View Poster<\/a><\/p>\n

View Abstract<\/a> – View on IEEEXplore\u00ae<\/a><\/p>\n<\/div><\/div><\/div>

August 20<\/div><\/div>
<\/i><\/div>
<\/div>
Binary Translation Framework Update #2<\/div>

Tagged version v0.2<\/a> of Binary Translation Framework capable of generating HDL from the developed ANTLR based intermediate representations of the detected binary segments, for MicroBlaze and ARMv8!<\/p>\n<\/div><\/div><\/div>

August 18<\/div><\/div>
<\/i><\/div>
<\/div>
Journal Publication #8<\/div>
\"Journal<\/a><\/div>

N. Paulino, J. C. Ferreira and J. M. P. Cardoso, “Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets<\/em>“, in IEEE Access, vol. 8, pp. 152286-152304, 2020, doi: 10.1109\/ACCESS.2020.3017552.<\/p>\n

View on IEEEXplore\u00ae<\/a><\/p>\n<\/div><\/div><\/div>

July 30<\/div><\/div>
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<\/div>
Data #3<\/div>

Nuno Paulino, 2020, “A Batch of Integer Data Sets for Clustering Algorithms”<\/em><\/p>\n

View on ResearchGate<\/a><\/p>\n<\/div><\/div><\/div>

July 20<\/div><\/div>
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<\/div>
Utility #1<\/div>
\"Utility<\/a><\/div>

Nuno Paulino, 2020, “A Generator of Randomly Correlated N-Dimentional Clusters<\/em>”<\/p>\n

View on ResearchGate<\/a><\/p>\n<\/div><\/div><\/div>

June 8<\/div><\/div>
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<\/div>
Journal Publication #7<\/div>

Mario V\u00e9stias, Rui P. Duarte, Jos\u00e9 T. de Sousa, Hor\u00e1cio C. Neto,”A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs<\/em>“, in IEEE Access<\/em>, vol. 8, pp. 107229-107243, 08 June 2020<\/p>\n

View on IEEEXplore\u00ae<\/a><\/p>\n<\/div><\/div><\/div>

May 18<\/div><\/div>
<\/i><\/div>
<\/div>
Journal Publication #6<\/div>

Mario V\u00e9stias, Rui P. Duarte, Jos\u00e9 T. de Sousa, Hor\u00e1cio C. Neto, “Moving Deep Learning to the Edge<\/em>“,\u00a0Algorithms<\/em> 2020, 13<\/em>, 12, 18 May 2020, https:\/\/doi.org\/10.3390\/a13050125<\/p>\n

View on MDPI\u00ae<\/a><\/p>\n<\/div><\/div><\/div>

May 14<\/div><\/div>
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<\/div>
Journal Publication #5<\/div>

M\u00e1rio V\u00e9stias, Rui P. Duarte, Jos\u00e9 T. de Sousa, Hor\u00e1cio C. Neto, “A fast and scalable architecture to run convolutional neural networks in low density FPGAs”, Microprocessors and Microsystems, Volume 77, 2020, 14 May 2020<\/p>\n

View on Elsevier<\/a><\/p>\n<\/div><\/div><\/div>

March 25<\/div><\/div>
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<\/div>
Journal Publication #4<\/div>

Valter M\u00e1rio, Jo\u00e3o D. Lopes, Mario V\u00e9stias, Jos\u00e9 T. de Sousa, “Implementing CNNs Using a Linear Array of Full Mesh CGRAs<\/em>“, In: Rinc\u00f3n F., Barba J., So H., Diniz P., Caba J. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications<\/em>. ARC 2020. Lecture Notes in Computer Science, vol 12083. Springer, Cham.<\/p>\n

View on Springer\u00ae<\/a><\/p>\n<\/div><\/div><\/div>

March 9<\/div><\/div>
<\/i><\/div>
<\/div>
Demo Booth at DATE2020 (Virtual)<\/div>
\"Demo<\/a><\/div>

Nuno Paulino and Jo\u00e3o C. Ferreira, 2020, “A Binary Translation Framework for Automated Hardware Generation”<\/em>, Demo Booth at Design Automation and Test in Europe (DATE), Grenoble, France, 9 – 13 March 2020<\/p>\n

View Demo Video<\/a> – View on IEEEXplore\u00ae<\/a><\/p>\n

View Poster<\/a> – View Abstract<\/a><\/p>\n<\/div><\/div><\/div>

February 10<\/div><\/div>
<\/i><\/div>
<\/div>
Short Keynote<\/div>

Presentation of a short keynote regarding published journal paper “Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey<\/em>“, at the 16th edition of national conference REC, held at the “Instituto Superior T\u00e9cnico”, Lisbon.<\/p>\n

View Conference Page<\/a> – View Presentation<\/a><\/p>\n<\/div><\/div><\/div>

February 9<\/div><\/div>
<\/i><\/div>
<\/div>
Data #2<\/div>

Nuno Paulino, Jo\u00e3o C. Ferreira, and Jo\u00e3o M. P. Cardoso, \u201cA Breakdown of Binary Acceleration Approaches and Systems\u2033<\/em>, 2020<\/p>\n

View on ResearchGate<\/a><\/p>\n<\/div><\/div><\/div>

February 9<\/div><\/div>
<\/i><\/div>
<\/div>
Data #1<\/div>
\"Data<\/a><\/div>

Nuno Paulino, Jo\u00e3o C. Ferreira, and Jo\u00e3o M. P. Cardoso, “A Dataset for Desktop Processor Characteristics from 1970 to 2019″<\/em>, 2020<\/p>\n

View on ResearchGate<\/a><\/p>\n<\/div><\/div><\/div>

February 8<\/div><\/div>
<\/i><\/div>
<\/div>
Journal Publication #3<\/div>
\"Journal<\/a><\/div>

Nuno Paulino, Jo\u00e3o Canas Ferreira, and Jo\u00e3o M. P. Cardoso. 2020. “Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey”.<\/em> ACM Comput. Surv. 53, 1, Article 6 (February 2020), 36 pages. DOI:https:\/\/doi.org\/10.1145\/3369764<\/p>\n

View on ACM Digital Library<\/a><\/p>\n<\/div><\/div><\/div>

January 23<\/div><\/div>
<\/i><\/div>
<\/div>
Binary Translation Framework Update #1<\/div>
\"Binary<\/a><\/div>

Tagged version v0.1<\/a> of Binary Translation Framework capable of generating graph visualizations and profile data for detected binary instruction segments for 32-bit MicroBlaze and ARMv8 ISAs. Supported segments include static and trace frequent instruction sequences, and static basic blocks!<\/p>\n<\/div><\/div><\/div>

2019<\/span><\/div><\/div>
November 7<\/div><\/div>
<\/i><\/div>
<\/div>
Conference Publication #2<\/div>
\"Conference<\/a><\/div>

M. P. V\u00e9stias, R. Policarpo Duarte, J. T. de Sousa and H. Neto, \u201cHybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA\u201d<\/em>, 2019 29th International Conference on Field Programmable Logic and Applications (FPL), Barcelona, Spain, 2019, pp. 350-353. doi: 10.1109\/FPL.2019.00062<\/p>\n

View on IEEEXplore\u00ae<\/a><\/p>\n<\/div><\/div><\/div>

September 19<\/div><\/div>
<\/i><\/div>
<\/div>
Journal Publication #2<\/div>

Mario V\u00e9stias, Rui P. Duarte, Jos\u00e9 T. de Sousa, Hor\u00e1cio C. Neto, “Fast Convolutional Neural Networks in Low Density FPGAs Using Zero-Skipping and Weight Pruning<\/em>“, Electronics<\/em> 2019, 8<\/em>, 1321<\/p>\n

View on MDPI<\/a><\/p>\n<\/div><\/div><\/div>

September 17<\/div><\/div>
<\/i><\/div>
<\/div>
Creation of Code Repository for Binary Translation Tools<\/div>

Creation of GitHub repository for implementation of Binary Translation Framework.<\/p>\n

See Repositories page<\/a> – See repository on GitHub<\/a><\/p>\n<\/div><\/div><\/div>

May 1<\/div><\/div>
<\/i><\/div>
<\/div>
Conference Publication #1<\/div>
\"Conference<\/a><\/div>

L. Fiolhais, F. Gon\u00e7alves, R. P. Duarte, M. V\u00e9stias and J. T. de Sousa, \u201cLow Energy Heterogeneous Computing with Multiple RISC-V and CGRA Cores\u201d<\/em>, 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 2019, pp. 1-5. doi: 10.1109\/ISCAS.2019.8702538<\/p>\n

View on IEEEXplore\u00ae<\/a><\/p>\n<\/div><\/div><\/div>

February 14<\/div><\/div>
<\/i><\/div>
<\/div>
Short Keynote<\/div>

Presentation of a short keynote regarding published journal paper “Dynamic Partial Reconfiguration of Customized Single-Row Accelerators”<\/em>,<\/em> at the 15th edition of national conference REC<\/em>, held at the University of Minho, Guimar\u00e3es.<\/p>\n

View Conference Page<\/a> – View Presentation<\/a><\/p>\n<\/div><\/div><\/div>

2018<\/span><\/div><\/div>
October 23<\/div><\/div>
<\/i><\/div>
<\/div>
Journal Publication #1<\/div>
\"Journal<\/a><\/div>

N. M. C. Paulino, J. C. Ferreira and J. M. P. Cardoso, “Dynamic Partial Reconfiguration of Customized Single-Row Accelerators”<\/em>, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 1, pp. 116-125, Jan. 2019.<\/p>\n

View on IEEEXplore\u00ae<\/a><\/p>\n<\/div><\/div><\/div>

October 10<\/div><\/div>
<\/i><\/div>
<\/div>
Project Start<\/div>

Start of project!<\/p>\n<\/div><\/div><\/div>\t\t\t\t\t<\/div>\n\t\t\t\t\t

<\/div>\n\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t<\/div>\n\t\t\t","protected":false},"excerpt":{"rendered":"","protected":false},"author":4,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-213","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/pepcc.inesctec.pt\/index.php?rest_route=\/wp\/v2\/pages\/213","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pepcc.inesctec.pt\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/pepcc.inesctec.pt\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/pepcc.inesctec.pt\/index.php?rest_route=\/wp\/v2\/users\/4"}],"replies":[{"embeddable":true,"href":"https:\/\/pepcc.inesctec.pt\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=213"}],"version-history":[{"count":12,"href":"https:\/\/pepcc.inesctec.pt\/index.php?rest_route=\/wp\/v2\/pages\/213\/revisions"}],"predecessor-version":[{"id":695,"href":"https:\/\/pepcc.inesctec.pt\/index.php?rest_route=\/wp\/v2\/pages\/213\/revisions\/695"}],"wp:attachment":[{"href":"https:\/\/pepcc.inesctec.pt\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=213"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}