{"id":207,"date":"2019-01-14T16:37:06","date_gmt":"2019-01-14T16:37:06","guid":{"rendered":"http:\/\/pepcc.inesctec.pt\/?page_id=207"},"modified":"2020-09-01T13:12:19","modified_gmt":"2020-09-01T13:12:19","slug":"challenges","status":"publish","type":"page","link":"https:\/\/pepcc.inesctec.pt\/?page_id=207","title":{"rendered":"Project Activities"},"content":{"rendered":"\t\t
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Project Activities<\/h1>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Background<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Modern embedded systems (ES) and HPC systems must operate under evermore similar requirements or constraints, which has pressured both domains into increasingly heterogeneous systems. While ES are put under increasing load by complex applications, HPC systems are struggling to provide power-efficiency as they scale [10].\u00a0 The use of specialized and potentially self-adaptive hardware which targets specific and very demanding tasks has been identifies as a possible solution to address these issues for both domains [9].<\/p>\n

Many applications in both domains have a small number of regular computational kernels that account for most of the execution time and energy consumption. The manual development of accelerators requires significant design time and hardware expertise. However, it is vital to not compromise developer productivity by demanding manual hardware development and source code alterations.<\/p>\n

The PEPCC project was created from the converging scientific works of its team members<\/strong>, which collectively address the issue of how to design systems, in the embedded and high-performance computing (HPC) domains, which provide computation that is both fast and power-efficient, by means of heterogenous computing architectures and respective compilation methods which target them [1-8].<\/p>\n<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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Objectives and Research Plan<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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PEPPC aims to address the highlighted issues regarding efficient computation by furthering exploring the research paths of its constituent team members<\/a> by structuring said efforts into a convergent, coherent, and structured<\/strong> overarching research plan.<\/p>\n

Given the convergence of requirements between ES and HPC, the mapping of computations to specialized or reconfigurable circuits at runtime (dynamic mapping) has growing importance as a research goal. An efficient implementation of this capability will\u00a0allow for hardware resources of reconfigurable circuits to be exploited by any application running in the system,\u00a0 addressing both power efficiency and performance concerns, and contribute to code portability and performance scalability. If effective and efficient, runtime mapping schemes will increase productivity by offloading demanding computation to specialized hardware with minimal developer intervention, and based on actual application workload. Exploiting runtime information is paramount in order to fulfill this goal.<\/p>\n

The project is divided into several activities, whose joint goal is too:<\/p>\n<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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Improve performance and power efficiency of regular computational kernels in ES and HPS systems,\u00a0by efficient runtime mapping of computations to specialized CGRA, while ensuring the most transparency to the application developer.<\/em><\/strong><\/p>\n<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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This will be accomplished by researching advanced binary trace analysis<\/strong> methods for Just-in-Time hardware generation and (re-)configuration. Information from this process will also be used to dynamically adapt existing CGRAs by hardware modification, or to select existing specialized CGRAs based on the workload to process. To study solutions which balance specialization and programmability, the project will also further develop the existing Versat architecture [5]. Finally, the binary analysis and hardware generation methods to be developed in the aforementioned activities will require studying methods though which they can be exploited and integrated into ES and HPC systems.<\/p>\n<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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A1.Advanced Trace Analysis for JIT Hardware Generation<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t
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Extracting more information from the binary traces will enable the identification and exploitation of more parallelism than currently exposed by static analysis. Binary traces called Megablocks [2,3] will be used as the starting point for the representation of knowledge about repetitive instruction traces; the model will be expanded to include the additional extracted information. The project will address these specific issues: loop dependency analysis, memory access disambiguation<\/strong> and detection of streaming access patterns, and data specialization.<\/strong><\/p>\n<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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Milestones<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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